ETA International CET: Learn Circuit-State Reasoning

The CET rewards a specific habit: reading a schematic as a set of electrical states rather than a collection of part symbols. A resistor is not just 1 kΩ; it is 1 kΩ under this supply, this load, and this fault condition. Build your study around that idea. Work every practice problem twice — once to compute the answer and once to predict what your meter would display if one component opened or shorted. The sections below apply that method across DC networks, AC behavior, semiconductors, digital logic, instruments, and troubleshooting, with two worked scenarios and a self-check rubric.

Series-Parallel Networks: Computing One Answer vs. Predicting Every Fault State

Reduce the network to find one correct set of voltages and currents, then treat each open or short as a brand-new circuit to re-solve. That second skill — state prediction — is what scenario-style questions exercise.

Start every network problem by labeling nodes and polarities before touching numbers. Identify series strings and parallel nodes, combine resistances step by step, then back-solve for branch currents. Trace one chain fully: a 12 V source feeds R1 = 1 kΩ in series with a parallel pair of two 2 kΩ resistors. The pair combines to 1 kΩ, total resistance is 2 kΩ, total current is 6 mA, the parallel node sits at 6 V, and each branch carries 3 mA. Writing the node voltage and each branch current at every step turns a one-shot calculation into a map you can reuse.

The fault-state map is where the trap lives. A meter reading of 0 V across a component does not prove that component is shorted — in a series string where current has stopped, every good component reads near 0 V. Conversely, an open component in a series path drops the full supply voltage across itself. In parallel branches the logic flips: an open branch does not change the voltage across the others, but a shorted branch collapses the node and spikes total current. Internalize the table below, then re-derive it yourself with numbers until the reasoning, not the table, is what you recall.

Reactance vs. Resistance: What Changes When the Source Starts Alternating

Resistance opposes current the same way at any frequency and dissipates energy. Capacitive and inductive reactance change with frequency and shift the current's phase, so AC analysis must combine them vectorially as impedance.

Use the two frequency laws as decision tools. Capacitive reactance falls as frequency rises (Xc = 1/2πfC), so a capacitor blocks DC but passes higher frequencies more easily — the basis of coupling and filtering. Inductive reactance rises with frequency (XL = 2πfL), so an inductor passes DC but impedes fast changes. Run one concrete number: a 1 µF capacitor at 1 kHz presents roughly 159 Ω of reactance, and that value drops by half at 2 kHz. Impedance is the vector sum of resistance and reactance, never a plain arithmetic sum, because of the 90-degree phase relationship.

Time-domain behavior matters just as much as frequency-domain behavior for technician-level reasoning. The RC time constant τ = RC tells you how fast a capacitor charges: about 63% of the final voltage after one τ, and effectively settled after about five τ. Trace the consequences: a coupling capacitor sized for audio passes the signal while blocking the DC bias point; a power-supply filter capacitor must hold charge between rectifier peaks. When you study a filter or coupling circuit, state explicitly whether the capacitor's job is to block DC, pass AC, or store energy — the same component plays all three roles in different places.

Diode, BJT, and FET: Three Devices, Three Different Control Rules

Each device answers a different control question. A diode conducts one way, a BJT is controlled by base current, and a FET is controlled by gate voltage with essentially no gate current. Learn the control rule before the applications.

A silicon diode conducts in forward bias once the junction drop reaches roughly 0.7 V and blocks in reverse — that one-way behavior makes it a rectifier, a clamp, and a protection element. A bipolar junction transistor adds a control terminal: base current, flowing through a forward-biased base-emitter junction, allows a much larger collector current, with the ratio described by beta. The key structural fact is that the base-emitter junction is itself a diode, so bias design is about holding that junction slightly forward while keeping the transistor out of saturation when linear operation is wanted.

A field-effect transistor replaces base current with gate voltage: the gate draws essentially no steady current, and the gate-to-source voltage sets the channel conduction. That difference drives real design choices — a FET stage loads a high-impedance source far less than a BJT stage, because the BJT's base needs continuous current. Carry this into fault reasoning too: measuring an unexpected base-emitter voltage in-circuit points first at the bias network feeding the base, not automatically at the transistor itself, because the surrounding resistors set the junction's operating point.

Practice comparing the three on the same schematic: mark where a signal enters, which terminal controls the output, and what a multimeter would show at each junction in normal operation. Then flip one condition — a bias resistor open, or the supply absent — and restate the readings. Device knowledge that is stored as a control rule plus expected readings transfers to scenario questions; device knowledge stored as isolated definitions does not.

Digital Logic: Boolean Answers vs. What the Probe Shows at the Pin

Boolean algebra gives the steady-state logic expression; gate-level tracing asks what a logic probe would actually show at each pin, including the effect of an open or unconnected input. Study the two as separate skills.

Master truth tables and De Morgan's theorems until converting between AND/OR/NOT forms and NAND/NOR-only implementations is mechanical. For example, an OR function is equivalent to a NAND with both inputs inverted, and that identity is how real circuits are built when only one gate type is available. Practice by writing the Boolean expression for a small combinational network, simplifying it, then redrawing the simplified version and confirming the truth tables match. This is the algebra half, and it is fully verifiable on paper.

The tracing half adds physical reality. A gate output is high, low, or — in a faulted circuit — disconnected, and an open input behaves differently depending on the logic family and circuit design, so never assume a floating input's level without justification. Run this mini-exercise on a simulator or breadboard: wire a two-input NOR gate with one input to a toggle switch and the other to a jumper you can remove. Predict the output for switch-high, switch-low, and jumper-removed states before energizing, then probe and compare. If your prediction and observation disagree, the discrepancy is the lesson — write down which assumption failed.

Instrument Readings as Evidence: A 0 V Reading Is Not a Diagnosis

A measurement is evidence about the circuit's state, not a verdict about a component. Match the instrument function to the question — voltage, current, or resistance — and interpret the reading within the circuit's conditions.

Fix the connection rules first: a voltmeter goes in parallel across the element, an ammeter goes in series and interrupts the circuit, and resistance measurements are valid only on a de-energized circuit. Understand meter loading too — a meter's own impedance slightly changes the node it touches, which matters most on high-impedance divider points. These rules are not bureaucracy; each one exists because violating it produces either a wrong reading or a new fault, and exam scenarios are built on exactly that kind of judgment.

Worked scenario 1: a 12 V supply feeds R1 = 1 kΩ in series with R2 = 1 kΩ, and the meter across R2 reads 0 V. The plausible mistake is concluding R2 is shorted and replacing it. The better decision is to reason from the state: with no current flowing, every good series component reads near 0 V, so move upstream — the meter across R1 shows about 12 V, identifying R1 as the open element. It matters because the first interpretation discards a good part and leaves the fault in place, while the second uses two readings to localize the open in one step. The lesson generalizes: full supply voltage across a series component points at an open in it; near-zero voltage across a component in a dead string proves nothing about that component.

Signal-Flow Troubleshooting: Divide the Path Instead of Swapping Parts

Follow the signal from a known-good input toward the failure and split the path at each stage, using measurements to keep or discard half of the remaining suspects. Hypothesis-driven checks beat part swapping on both time and safety.

Worked scenario 2: a linear power supply feeds an audio amplifier, the DC output measures a normal 12 V on the DMM, but the amplifier hums. The plausible mistake is replacing the rectifier bridge, because 'power supply hum' suggests rectification trouble. The better decision is to change the measurement, not the parts: switch the DMM to its AC voltage range across the output, or view it on a scope, and observe a ripple of a few volts peak-to-peak — evidence that the filter capacitor has lost most of its capacitance. It matters because the DC average reading masks the ripple entirely, so the instrument function you choose determines whether you diagnose the supply or guess at it. Replace the filter capacitor and the symptom should disappear; replace the bridge and it will not.

Practical exercise with a self-check rubric: on a simulator or breadboard, build a two-stage circuit — a resistive voltage divider biasing a transistor switch that drives an LED. Predict the LED state and key node voltages before energizing. Then have someone (or your simulator) inject one fault at a time: an open base resistor, a shorted collector-emitter path, and a reversed LED. Score yourself against this rubric: (1) all three injected faults identified in three measurements or fewer, with the discriminating measurement named; (2) predictions matched observed behavior before each fault hunt; (3) you can explain why the misleading reading in each case did not prove the innocent component bad. Treat the score as a learning milestone for tracking concept gaps, not as a prediction of any exam result.

Safety Judgment, Documentation Habits, and Readiness Checks for Exam Week

Safety and documentation are applied judgment, not slogans: de-energize before resistance checks, assume charged capacitors, and record measurements in signal order. Close your preparation with the readiness checks below.

Build safety reasoning into every practice scenario rather than studying it separately. On paper, before each fault hunt, state the safe sequence: power down and verify the absence of voltage before any resistance measurement, treat filter capacitors as potentially charged until discharged through a safe bleeder path, and keep measurement leads and hands clear of energized high-current points. Document as you would in a working job: each reading, the instrument function used, the measurement point, and the conclusion it supported. A written measurement trail is what lets you backtrack when a hypothesis collapses, and practicing it makes the discipline automatic instead of an afterthought.

Structure the final weeks as an adaptable sequence rather than a fixed calendar. Phase one: schematic reading and series-parallel fault-state drills. Phase two: reactance, impedance, and time-constant problems. Phase three: the diode/BJT/FET control rules with expected-reading tables. Phase four: digital algebra and gate tracing. Phase five: instrument selection and the two scenarios above, repeated with different values. Phase six: mixed timed sets plus an error log you re-test after 48 hours. Finish only when the readiness checks below all pass, and keep an error log of every misread circuit so your last week targets known gaps instead of comfortable material.

• Solve ten mixed series-parallel problems, each including one injected open or short, without notes, and state the meter readings the fault would produce
• For any diode, BJT, or FET symbol, state its control rule and one expected junction or pin reading in one sentence
• For five fault symptoms, name the instrument function, the measurement point, and why that combination discriminates between suspects
• Redraw a mixed-logic circuit as a NAND-only implementation and verify the truth tables match
• Re-test every entry in your error log after 48 hours and retire only the entries you now get right from a cold start

References and further reading

Use these references to explore the concepts and check the latest information from the relevant organizations.

• eta-i.org

Continue your preparation

• Eta International Electronics Technician Cet
• Study Guides